View HD74LS123_4242244.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HD74LS123
Dual Retriggerable Monostable Multivibrators (with Clear)
REJ03D0429-0200 Rev.2.00 Feb.18.2005 This d-c triggered multivibrator features output pulse width control by three method. The basic pulse time is programmed by selection of external resistance and capacitance values. Once triggered, the basic pulse width may be extended by retriggering the gated low-level -active (A) or high-level active (B) inputs, or be reduced by use of the overriding clear. Figure 1 illustrates pulse control by retriggering and early clear. This device is provided enough Schmitt hysteresis to ensure jitter-free triggering from the B input with transition rates as slow as 0.1 mV/ns.
Features
* Ordering Information
Part Name HD74LS123P HD74LS123FPEL HD74LS123RPEL Package Type DILP-16 pin SOP-16 pin (JEITA) SOP-16 pin (JEDEC) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) Package Abbreviation P FP Taping Abbreviation (Quantity) -- EL (2,000 pcs/reel) EL (2,500 pcs/reel)
PRSP0016DG-A RP (FP-16DNV) Note: Please consult the sales office for the above package availability.
A = "L" Clear = "H" B
Retrigger Pulse "H" "L" tw + tPLH "H"
Q
tw Output without retrigger A = "L" "H"
"L"
B "L" "H" Clear "L" "H" Q "L" Output without clear
Figure 1
Typical Input / Output Pulse
Rev.2.00, Feb.18.2005, page 1 of 8
HD74LS123
Pin Arrangement
1A 1B 1CLR 1Q 2Q 2Cext 2Rext/Cext GND
1 2 3 4 5 Q 6 7 8 Q CLR CLR Q
16 15 14 Q 13 12 11 10 9
VCC 1Rext/Cext 1Cext 1Q 2Q 2CLR 2B 2A
(Top view)
Function Table
Inputs Clear A1 L X X H X X H L H L Notes: H; high level, L; low level, X; irrelevant ; transition from low to high level ; transition from high to low level ; one high-level pulse ; one low-level pulse Outputs B2 X X L H H Q L L L Q H H H
Block Diagram (1/2)
External parameter
Cext A B
Rext /Cext
VCC Q Q
Q Clear Clear
Q
Rev.2.00, Feb.18.2005, page 2 of 8
HD74LS123
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Input pulse width External timing resistance External capacitance Wiring capacitance at Rext/Cext terminal A, B CLR "H" "L" "L" Rext Cext -- tw (in) Symbol VCC IOH IOL Topr Min 4.75 -- -- -20 40 40 40 5 Typ 5.00 -- -- 25 -- -- -- -- Non restriction -- 50 pF Max 5.25 -400 8 75 -- -- -- 260 Unit V A mA C ns ns ns k
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL IIH IIL II Short-circuit output current Supply current** Input clamp voltage IOS ICC VIK min. 2.0 -- 2.7 -- -- -- -- -- -20 -- -- typ.* -- -- -- -- -- -- -- -- -- 12 -- max. -- 0.8 -- 0.4 0.5 20 -0.4 0.1 -100 20 -1.5 Unit V V V V A mA mA mA mA V Condition
Input current
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = -18 mA
* VCC = 5 V, Ta = 25C ** With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is applied to clock. Note: To measure VOH at Q, VOL at Q, or IOS at Q, ground Rext / Cext, apply 2 V to B and clear, and pulse A from 2 V to 0 V.
Rev.2.00, Feb.18.2005, page 3 of 8
HD74LS123
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Symbol tPLH tPHL tPLH tPHL tPLH tPHL t(out)min Output pulse width t(out) A, B Inputs A B CLR Outputs Q Q Q Q Q Q Q Q min. -- -- -- -- -- -- -- 4 typ. 23 32 23 34 20 28 116 4.5 max. 33 45 44 56 27 45 200 5 Unit Condition
Propagation delay time
ns
Cext = 0, Rext = 5 k, CL = 15 pF, RL = 2 k
s
Cext = 1000 pF, Rext = 10 k, CL = 15 pF, RL = 2 k
Typical Application Data for HD74LS123
For pulse widths when Cext 1000 pF, See Figure 3. The output pulse is primarily a function of the external capacitor and resistor. For Cext > 1000 pF, the output pulse width (tw) is defined as: tw(out) = K * Rext * Cext; See Figure 4.
VCC
Rext
+ -
Cext Rext (k) Cext (pF) tw(out) (ns)
to Cext
to Rext/Cext
Figure 2
Timing Component Connections
100,000
Output pulse width tw (ns)
Rext = 160k
10,000
1,000
Rext = 80k 40k 20k 10k 5k
100
10 1 10
100
1,000
External capacitance Cext (pF)
Figure 3
Typical Output Pulse Width (Cext 1000 pF)
Rev.2.00, Feb.18.2005, page 4 of 8
HD74LS123
0.5
A coefficient of output pulse width K
0.4 0.3 0.2 0.1 0
VCC = 5V Ta = 25C
103 2 3
5 7104 2 3
5 7105 2 3
5 7106 2 3
5 7107
Timing capacitance Cext (pF)
Figure 4
Cext vs. K (Cext > 1000 pF)
Rev.2.00, Feb.18.2005, page 5 of 8
HD74LS123
Testing Method
Test Circuit
VCC A1 Input P.G. Zout = 50 Cext Rext /Cext VCC RL Q CL Output Q CLR Input P.G. Zout = 50 Q CLR Same as Load Circuit 1. Load circuit 1 Output Q
Cext B1 Input
Rext /Cext
P.G. Zout = 50
Notes:
1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).
Waveform
tw (in) A 40ns 1.3V 1.3V tw (in) 40ns B 1.3V 1.3V 0V tw (in) 40ns 1.3V tw (in) 40ns tw (CLR) 40ns Clear 1.3V 1.3V 0V tPLH Q 1.3V tPHL tPLH Q 1.3V tPHL 1.3V tPHL 1.3V tPLH VOH 1.3V tw (out) tw (out) 1.3V 1.3V VOL VOH 1.3V VOL 3V 1.3V 0V 3V 3V
Note:
Input pulse; tTLH 15 ns, tTHL 6 ns.
Rev.2.00, Feb.18.2005, page 6 of 8
HD74LS123
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.2.00, Feb.18.2005, page 7 of 8
HD74LS123
JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A Previous Code FP-16DNV MASS[Typ.] 0.15g
*1
D 9
F
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
Index mark
*2
E
HE
c
Reference Symbol
Dimension in Millimeters Min Nom 9.90 3.95 Max 10.30
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c c
1
0.10
0.14
0.25 1.75
0.34
0.40
0.46
0.15
0.20
0.25
HE
0 5.80 6.10 1.27
8 6.20
A
A1
L y
e x y
0.25 0.15 0.635 0.40
1
Detail F
Z L L 0.60 1.08
1.27
Rev.2.00, Feb.18.2005, page 8 of 8
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .2.0

▲Up To Search▲

Price & Availability of HD74LS123

	To Download HD74LS123 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .